The miss rate of L2 in a two-level cache heirarchy1

 

Consider a two-level cache hierarchy with L1L1 and L2L2 caches. An application incurs 1.41.4 memory accesses per instruction on average. For this application, the miss rate of L1L1 cache is 0.10.1; the L2L2 cache experiences, on average, 77 misses per 10001000instructions. The miss rate of L2L2 expressed correct to two decimal places is ________.

1Comment
shivani @shivani1234
27 Apr 2017 07:19 pm

Right question should be:

Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________. 

Ans: 

Since , it is given in question that for 1 instruction it takes 1.4 memory access(ma)

So, for 1000 instr. it will take =1000* 1.4 ma= 1400 ma

Now , it is given for l1 cache miss rate(mr) = 0.1

and since , we know mr=no. of misses/total no. of ma

so, 0.1=no. of misses/1400

thus, no. of misses of l1 =140

As , we know when there is miss in l1 , we search for data in l2

so, now for l2 cache total no. of ma=140, and it is given there is 7 miss

so , mr for l2 cache=7/140=1/20=0.05