two-level paging scheme

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?
(A) 645 nanoseconds
(B) 1050 nanoseconds
(C) 1215 nanoseconds
(D) 1230 nanoseconds

3Comments
Arjun @arjunsinghra
27 Jan 2017 04:10 am

EAIET= CPU Time + ( 90%(TLBHIT) +10%(TLBMISS) )

TLB HIT=pagefault rate(page fault service time + 2 * main memory access time)+(1-pagefault rate)(2 * main memory access time)

TLB HIT=P(PFST + 2MM) + (1-P)(2MM)

TLB HIT=P(PFST) + P(2MM) + 2MM-P(2MM)

TLB HIT=P(PFST) + 2MM

TLB HIT=(1/10,000)(8*106) +2*150

TLB HIT=1100ns

..............................................................................................................................

TLB MISS=pagefault rate(page fault service time +2 * page table access time + 2 * main memory access time)+(1-pagefault rate)(2*page table access time + 2 * main memory access time)

TLB MISS=P(PFST + 4MM) + (1-P)(4MM)

TLB MISS=P(PFST) + P(4MM) + 4MM-P(4MM)

TLB MISS=P(PFST) + 4MM

TLB MISS=(1/10,000)(8*106) +4*150

TLB MISS=1400ns

EAIET= CPU Time + ( 90%(TLBHIT) +10%(TLBMISS) )

EAIET= 100 + ( 90%(1100) +10%(1400) )

EAIET= 1230ns

Shraddha @shraddhagami
27 Jan 2017 09:22 am
Rahul @rahul55523
27 Jan 2017 11:33 am

thank you