what is the duration of glitch for Q before it becomes stable?

Consider the logic circuit given below.

The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?

  1. 5
  2. 11
  3. 16
  4. 27

 

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5Comments
vaishali @vaisbhat
24 Apr 2017 11:47 am

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns. 

shweta @shweta1920
25 Apr 2017 10:43 am

thank u...

vaishali @vaisbhat
24 Apr 2017 11:48 am

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns. 

Sumit Verma @sumitkgp
24 Apr 2017 12:59 pm

You can search "Hazards in combinational circuits".

shweta @shweta1920
25 Apr 2017 10:45 am

thank u .....